1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly a mode setting circuit for generating a mode setting signal for selecting a particular operational mode in response to an input signal from a mode setting pad.
2. Description of the Related Art
Recently, with the rapid expansion of practical applications for semiconductor memory devices, various design technologies have been developed for realizing several operational modes into one chip. A memory device including various operational modes necessarily requires a mode setting circuit for selecting a particular operational mode. For example, there is a known method for bonding a mode setting pad to an external supply voltage terminal or a ground voltage terminal so as to generate a mode setting signal for selecting a particular operational mode. The mode setting circuit is commonly connected to the mode setting pad to generate the mode setting signal upon detecting an input voltage applied to the mode setting pad. Such mode setting circuit activates the mode setting signal to select a predetermined operational mode when the mode setting pad is coupled to the supply voltage terminal, and inactivates the mode setting signal when the mode setting pad is separated from the supply voltage terminal.
Generally, the mode setting circuit includes a driver circuit and a discharge transistor with a small channel size. When the mode setting pad is coupled to the supply voltage terminal, the driver circuit activates the mode setting signal to the high level. On the other hand, when the mode setting pad is not coupled to the supply voltage terminal, the small sized discharge transistor discharges the voltage at the mode setting pad so as to inactivate the mode setting signal to the low level.
Referring to FIG. 1, a mode setting circuit according to the prior art includes a mode setting pad 100, a discharge transistor 105, and a driver circuit. The discharge transistor 105 has a source-drain channel connected between the mode setting pad 100 and the ground node, and a gate connected to an internal voltage VIN generated internally within a chip. Since the gate of the discharge transistor 105 is provided with the internal voltage VIN, the discharge transistor 105 is normally turned on. Further, the discharge transistor 105 has a very small channel size so as to discharge the voltage at the mode setting pad 100 into the ground node by way of the source-drain channel when the mode setting pad 100 is not coupled to the supply voltage terminal. When the mode setting pad 100 is coupled to the supply voltage terminal, the driver circuit transfers the voltage level at the mode setting pad 100 to an output terminal "OUT" of the mode setting circuit. The driver circuit generally includes a first inverter connected between the mode setting pad 100 and a node N1, and a second inverter connected to the node N1. The first inverter usually includes a pull-up PMOS transistor 101 and a pull-down NMOS transistor 102 serially connected between the supply voltage and the ground voltage. The second inverter includes a pull-up PMOS transistor 103 and a pull-down NMOS transistor 104 serially connected between the supply voltage and the ground node.
In operation, when the mode setting pad 100 is coupled to the supply voltage terminal, the first inverter generates the low level and the second inverter generates a mode setting signal OUT activated to the high level. In the meantime, the discharge transistor 105 is continuously turned on. However, since the channel size of the discharge transistor 105 is very small, the voltage at the mode setting pad 100 can be maintained at the high level.
On the other hand Alternatively, when the mode setting pad 100 is not coupled to the supply voltage terminal, the voltage at the mode setting pad 100 is discharged into the ground node through the source-drain channel of the pull-down transistor 105 which is normally turned on. Thus, the voltage at the mode setting pad 100 is firmly maintained at the low level. Then, the first inverter maintains the node N1 at the high level, and the second inverter inactivates the mode setting signal OUT to the low level.
In practice, however, problems may arise with this arrangement because the pull-down transistor 105 and the driver circuit often share the same ground node in order to minimize a layout area. Thus, when ground noise is generated from other circuits sharing the same ground node within the chip, the mode setting circuit may be adversely influenced. For example, if the ground node voltage rises above the threshold voltage Vth of the NMOS transistor due to the ground noises, the gate-source voltage Vgs of the pull-down NMOS transistor 102 becomes higher than the threshold voltage Vth of the NMOS transistor. Accordingly, the pull-down NMOS transistor 102 is undesirably turned on and the second inverter erroneously activates the mode setting signal OUT to the high level. In other words, the mode setting circuit may erroneously select a particular operational mode, even though the mode setting pad 100 is not coupled to the supply voltage terminal. Such misoperation may cause a fatal defect of the chip.